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M68AW128M
2 Mbit (128K x16) 3.0V Asynchronous SRAM
FEATURES SUMMARY

SUPPLY VOLTAGE: 2.7 to 3.6V 128K x 16 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIME: 55ns SINGLE BYTE READ/WRITE LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN PACKAGES - Compliant with Lead-Free Soldering Processes - Lead-Free Versions
Figure 1. Packages
44
1
TSOP44 Type II (ND)
BGA
TFBGA48 (ZB) 6 x 8mm
September 2004
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M68AW128M
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Figure 5. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.. . . . . . . . . . . . . 12 Figure 10.Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . 13 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 12.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 13.UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 14.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 15.TSOP44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . . 18 Table 10. TSOP 44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 16.TFBGA48 6x8mm - 6x8 Active Ball Array, 0.75mm pitch, Bottom View Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 11. TFBGA48 6x8mm - 6x8 Active Ball Array, 0.75mm pitch, Package Mechanical Data . . 19
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PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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M68AW128M
SUMMARY DESCRIPTION
The M68AW128M is a 2 Mbit (2,097,152 bit) CMOS SRAM, organized as 131,072 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW128M is available in TFBGA48 (0.75 mm pitch) and in TSOP44 Type II packages. In addition to the standard version, the packages are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes.
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
A0-A16 DQ0-DQ15 Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Upper Byte Enable Input Lower Byte Enable Input Supply Voltage Ground Not Connected Internally Don't Use as Internally Connected
17 A0-A16 W
16 DQ0-DQ15
E G W UB
E M68AW128M G UB LB
LB VCC VSS NC DU
VSS
AI04835b
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M68AW128M
Figure 3. TSOP Connections
A4 A3 A2 A1 A0 E DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 W A16 A15 A14 A13 A12
44 1 2 43 42 3 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 M68AW128M 12 33 13 32 14 31 15 30 16 29 28 17 27 18 26 19 25 20 24 21 22 23
AI04836b
A5 A6 A7 G UB LB DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC
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M68AW128M
Figure 4. TFBGA Connections (Top view through package)
1 2 3 4 5 6
A
LB
G
A0
A1
A2
NC
B
DQ8
UB
A3
A4
E
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSS
DQ11
NC
A7
DQ3
VCC
E
VCC
DQ12
NC
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
NC
A12
A13
W
DQ7
H
NC
A8
A9
A10
A11
DU
AI04837
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M68AW128M
Figure 5. Block Diagram
VCC VSS ROW DECODER A7 MEMORY ARRAY
A16
DQ15 UB
(8)
I/O CIRCUITS COLUMN DECODER
DQ0 LB
(8)
A0 (8) W E (8) LB G UB
A6
UB LB
AI04838
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M68AW128M
OPERATION
The M68AW128M has a Chip Enable power down feature which invokes an automatic standby mode whenever either Chip Enable is de-asserted (E = High) or LB and UB are de-asserted (LB and UB = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/ write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W, E, LB and UB as summarized in the Operating Modes table (see Table 2). Read Mode The M68AW128M is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data from eight or sixteen, depending on the status of the signal UB and LB, of the 2,097,152 locations in the static memory array, specified by the 17 address inputs. Valid data will be available at the eight or sixteen output pins within t AVQV after the last stable address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV, tGLQV or t BLQV) rather than the address. Data out Table 2. Operating Modes
Operation Deselected Deselected Lower Byte Read Lower Byte Write Output Disabled Upper Byte Read Upper Byte Write Word Read Word Write
Note: 1. X = VIH or VIL.
may be indeterminate at tELQX, tGLQX and tBLQX but data lines will always be valid at tAVQV. Write Mode The M68AW128M is in the Write mode whenever the W and E are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be deasserted during Address transitions for subsequent write cycles. When E (W) is Low, and UB or LB is Low, write cycle begins on the W (E)'s falling edge. When E and W are Low, and UB = LB = High, write cycle begins on the first falling edge of UB or LB. Therefore, address setup time is referenced to Write Enable, Chip Enable or UB/LB as t AVWL, tAVEL and tAVBL respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E, W or UB/LB. If the Output is enabled (E = Low, G = Low, LB or UB = Low), then W will return the outputs to high impedance within t WLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E, or for tDVBH before the
E VIH X VIL VIL VIL VIL VIL VIL VIL
W X X VIH VIL VIH VIH VIL VIH VIL
G X X VIL X VIH VIL X VIL X
LB X VIH VIL VIL X VIH VIH VIL VIL
UB X VIH VIH VIH X VIL VIL VIL VIL
DQ0-DQ7 Hi-Z Hi-Z Data Output Data Input Hi-Z Hi-Z Hi-Z Data Output Data Input
DQ8-DQ15 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Data Output Data Input Data Output Data Input
Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
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M68AW128M
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 3. Absolute Maximum Ratings
Symbol IO (1) PD TA TSTG TLEAD VCC VIO (3) Output Current Power Dissipation Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Supply Voltage Input or Output Voltage Parameter Value 20 1 -55 to 125 -65 to 150 (2) -0.5 to 4.6 -0.5 to VCC +0.5 Unit mA W C C C V V
plied. Exposure to Absolute Maximum Rating conditions for periods greater than 1s periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. One output at time not to exceed 1 second duration. 2. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 3. Up to a maximum operating VCC of 3.6V only.
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M68AW128M
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Parameter VCC Supply Voltage Range 1 Ambient Operating Temperature Range 6 Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Output Transition Timing Ref. Voltages -40 to 85C 30pF 3.0k 3.1k 1ns/V 0 to VCC VCC/2 VRL = 0.3VCC; VRH = 0.7VCC M68AW128M 2.7 to 3.6V 0 to 70C
Figure 6. AC Measurement I/O Waveform
Figure 7. AC Measurement Load Circuit
VCC
I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST CL Output Timing Reference Voltage VCC 0.7VCC 0.3VCC
AI05831
OUT
R2
0V
CL includes probe and 1 TTLcapacitance
AI05832
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M68AW128M
Table 5. Capacitance
Symbol CIN COUT Parameter(1,2) Input Capacitance on all pins (except DQ) Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 8 10 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. At TA = 25C, f = 1 MHz, VCC = 3.0V.
Table 6. DC Characteristics
Symbol ICC1 (1,2) ICC2 (3) Parameter Operating Supply Current Test Condition VCC = 3.6V, f = 1/tAVAV, IOUT = 0mA 70ns 55ns Min Typ Max 20 26 2 Unit mA mA mA
Operating Supply Current
VCC = 3.6V, f = 1MHz, IOUT = 0mA VCC = 3.6V, f = 0, E VCC -0.2V or LB=UB VCC -0.2V 0V VIN VCC 0V VOUT VCC -1 -1 2.2 -0.3 IOH = -1.0mA IOL = 2.1mA 2.4 5
ISB ILI ILO (4) VIH VIL VOH VOL
Note: 1. 2. 3. 4.
Standby Supply Current CMOS Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage
10 1 1 VCC + 0.3 0.6
A A A V V V
0.4
V
Average AC current, cycling at tAVAV minimum. E = VIL, LB OR/AND UB = VIL, V IN = V IL OR VIH. E 0.2V, LB OR/AND UB 0.2V, VIN 0.2V OR VIN V CC -0.2V. Output disabled.
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M68AW128M
Figure 8. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A16 tAVQV VALID tAXQX
DQ0-DQ7 and/or DQ8-DQ15
DATA VALID
AI04839
Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low.
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV A0-A16 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ15 tBLQV UB, LB tBLQX
AI04840
VALID tAXQX tEHQZ
tGHQZ
VALID tBHQZ
Note: Write Enable (W) = High.
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M68AW128M
Figure 10. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms
E, UB, LB ICC ISB tPU 50% tPD
AI03856
Table 7. Read and Standby Mode AC Characteristics
M68AW128M Symbol tAVAV tAVQV tAXQX (1) tBHQZ (2,3) tBLQV tBLQX (1) tEHQZ (2,3) tELQV tELQX (1) tGHQZ (2,3) tGLQV tGLQX (2) tPD tPU Read Cycle Time Address Valid to Output Valid Data hold from address change Upper/Lower Byte Enable High to Output Hi-Z Upper/Lower Byte Enable Low to Output Valid Upper/Lower Byte Enable Low to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable or UB/LB High to Power Down Chip Enable or UB/LB Low to Power Up Parameter 55 Min Max Min Max Max Min Max Max Min Max Max Min Max Min 55 55 5 20 55 5 20 55 5 20 25 5 55 0 70 70 70 5 25 70 5 25 70 5 25 35 5 70 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, t GHQZ is less than tGLQX , tBHQZ is less than tBLQX and t EHQZ is less than tELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
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M68AW128M
Figure 11. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVWH tELWH E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ15 DATA (1) DATA INPUT tDVWH tBLWH UB, LB
AI04841
tWHAX
tWHQX
DATA (1)
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
Figure 12. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVEH tAVEL E tWLEH W tEHDX DQ0-DQ15 DATA INPUT tDVEH tBLEH UB, LB
AI04842
tELEH
tEHAX
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M68AW128M
Figure 13. UB/LB Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVBH tELBH E tWLBH W tBHDX DQ0-DQ15 DATA (1) DATA INPUT tDVBH tAVBL UB, LB
AI04843
tBHAX
tBLBH
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
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M68AW128M
Table 8. Write Mode AC Characteristics
M68AW128M Symbol tAVAV tAVBH tAVBL tAVEH tAVEL tAVWH tAVWL tBHAX tBHDX tBLBH tBLEH tBLWH tDVBH tDVEH tDVWH tEHAX tEHDX tELBH tELEH tELWH tWHAX tWHDX tWHQX (1) tWLBH tWLEH tWLQZ (1,2) tWLWH Write Cycle Time Address Valid to LB, UB High Addess Valid to LB, UB Low Address Valid to Chip Enable High Address valid to Chip Enable Low Address Valid to Write Enable High Address Valid to Write Enable Low LB, UB High to Address Transition LB, UB High to Input Transition LB, UB Low to LB, UB High LB, UB Low to Chip Enable High LB, UB Low to Write Enable High Input Valid to LB, UB High Input Valid to Chip Enable High Input Valid to Write Enable High Chip Enable High to Address Transition Chip enable High to Input Transition Chip Enable Low to LB, UB High Chip Enable Low to Chip Enable High Chip Enable Low to Write Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to LB, UB High Write Enable Low to Chip Enable High Write Enable Low to Output Hi-Z Write Enable Low to Write Enable High Parameter 55 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Min 55 45 0 45 0 45 0 0 0 45 45 45 25 25 25 0 0 45 45 45 0 0 5 45 45 20 45 70 70 60 0 60 0 60 0 0 0 60 60 60 30 30 30 0 0 60 60 60 0 0 5 60 60 20 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
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M68AW128M
Figure 14. Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 3.6V VCC 2.7V
VDR > 1.5V tCDR E VDR - 0.2V or UB = LB VDR - 0.2V E or UB/LB tR
AI05805
Table 9. Low V CC Data Retention Characteristics
Symbol Parameter Test Condition VCC = 1.5V, E VCC -0.2V or UB = LB VCC -0.2V, f = 0 (3) 0 tAVAV E VCC -0.2V or UB = LB VCC -0.2V, f = 0 1.5 Min Typ 4.5 Max 9 Unit A ns ns V
ICCDR (1) Supply Current (Data Retention) Chip Deselected to Data tCDR (1,2) Retention Time tR (2) VDR (1) Operation Recovery Time Supply Voltage (Data Retention)
Note: 1. All other Inputs at V IH VCC -0.2V or VIL 0.2V. 2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V.
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M68AW128M
PACKAGE MECHANICAL
Figure 15. TSOP44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Outline
D
N
E1
E
1
N/2
ZD
b
e
A
A2 C CP A1 L
TSOP-d
Note: Drawing is not to scale.
Table 10. TSOP 44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data
Symbol Typ A A1 A2 b c D e E E1 L ZD CP N 44 18.410 0.800 11.760 10.160 0.500 0.805 0.350 0.120 - - - - 0.400 - 0 0.210 - - - - 0.600 - 5 0.100 44 0.7248 0.0315 0.4630 0.4000 0.0197 0.0317 0.050 0.950 millimeters Min Max 1.200 0.150 1.050 0.0138 0.0047 - - - - 0.0157 - 0 0.0083 - - - - 0.0236 - 5 0.0039 0.0020 0.0374 Typ inches Min Max 0.0472 0.0059 0.0413
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M68AW128M
Figure 16. TFBGA48 6x8mm - 6x8 Active Ball Array, 0.75mm pitch, Bottom View Package Outline
D FD FE SD D1
SE BALL "A1" E E1 ddd
e e A A1 b A2
BGA-Z26
Note: Drawing is not to scale.
Table 11. TFBGA48 6x8mm - 6x8 Active Ball Array, 0.75mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 8.000 5.250 0.750 1.125 1.375 0.375 0.375 7.900 - - - - - - 6.000 3.750 0.350 5.900 - 0.260 0.900 0.450 6.100 - 0.100 8.100 - - - - - - 0.3150 0.2067 0.0295 0.0443 0.0541 0.0148 0.0148 0.3110 - - - - - - 0.2362 0.1476 0.0138 0.2323 - Min Max 1.200 0.0102 0.0354 0.0177 0.2402 - 0.0039 0.3189 - - - - - - Typ Min Max 0.0472 inches
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M68AW128M
PART NUMBERING
Table 12. Ordering Information Scheme
Example: Device Type M68 Mode A = Asynchronous Operating Voltage W = 2.7 to 3.6V Array Organization 128 = 2 Mbit (128K x16) Option 1 M = 1 Chip Enable; Write and Standby from UB and LB Option 2 L = L-Die Speed Class 55 = 55 ns 70 = 70 ns Package ND = TSOP 44 Type II ZB = TFBGA48: 0.75 mm pitch Operative Temperature 1 = 0 to 70C 6 = -40 to 85C Shipping Blank = Standard Packing T = Tape & Reel Packing E = Lead-free and RoHS Package, Standard Packing F = Lead-free and RoHS Package, Tape & Reel Packing M68AW128 M L 55 ZB 6 T
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M68AW128M
REVISION HISTORY
Table 13. Document Revision History
Date July 2001 10-Dec-2001 18-Feb-2002 25-Mar-2002 17-June-2002 Version -01 -02 -03 -04 -05 First Issue. Document completely revised. Tables 2, 7, 8 and 9 clarified. Read and Standby Mode AC Characteristics table clarified (Table 7). Low VCC Data Retention Characteristics table clarified (Table 9). Minor changes. Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 05 equals 5.0). Part number modified. Lead-free package version added. tPU ad tPD updated in Table 7. Revision Details
09-Oct-2002
5.1
20-Apr-2004 24-Sep-2004
6.0 7.0
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M68AW128M
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